Huawei and Altera Collaborate to Develop 2.5D Packaging Integrated FPGA and Memory Unit

To break the memory bandwidth limitations of communications systems, Huawei and Altera will jointly develop and integrate FPGAs and memory cells in a 2.5D package. A senior Huawei scientist stated that although this technology is tricky, it is critical in the network. The announcement of this news made it impossible for the previous rumors about Huawei or the use of ASIC to cause Altera’s financial performance to perform poorly.

Although it took only 3 months, the new equipment will significantly reduce board space and improve performance. HUAWEI American research and development senior scientist Anwar A. Mohammed said, "The 2.5-D silicon intermediaries seem to be the most suitable for Internet companies - in fact, they are also the key."

A year ago, Xilinx announced its most dense FPGA using multi-mode parallel technology on a 2.5-D silicon interposer. At that time, Xilinx also had a great interest in the technology of the network company and planned for the product that will effectively combine FPGA and memory in the future.

Prior to the selection of the 2.5-D silicon interposer, Huawei spent more than one year and verified its effectiveness with no less than nine methods. In addition to Altera, Huawei also cooperated with Tezzaron, eSilicon, and Singapore Institute of Microelectronics. (As shown below)

The new 2.5-D device will replace 10 to 20 DDR memory and the ASIC currently being used by Huawei Systems, saving nearly 18% of board space and twice the bandwidth/watt. A wide range of I/O components will support eight 128-bit channels; the FPGA will include Huawei logic, PCI Express modules, and SERDES links of at least 3 Gbit/s.

Mohammed emphasized in the report that “the size of our line cards is constant, but if you want to integrate more and more features into it, then 2.5D is a powerful tool for this. Even if it is It is expensive, but integrating more functionality into the 2.5D silicon interposer will reduce the potential cost.Comms relies on faster serial-to-parallel transceivers to speed the transfer of data to memory, but the serial-to-parallel transceiver gain is at the latest The process technology is slower. The old solution no longer works."

To solve the 2.5D device problem, Huawei and its partners still face many challenges. Silicon interposers are still relatively expensive, and cost-footed glass and organic materials are not yet available. Engineers lack good molds, 2.5D CAD tools, enough credible data, testing strategies, rework and heat-treatment management.

In addition, the 2.5D supply chain is not mature enough and the scope of choice is not large. In addition, the return on investment is not clear. Mohammed said that everything is full of unknown and I hope everyone can share ideas and ensure the success of the technology. But even if it is unsuccessful, it is not surprising. After all, there are too many unknown factors. The 2.5D method is the intermediate step of transitioning from a through silicon via to a complete 3-D stacked die.