Programmable logic device CPLD changes: from PAL to PLD
After PAL is PLD, PLD and PAL devices are very similar, but with some other features, become a true programmable device, and more practical. A major advancement of this device from a simple PAL device is that it contains a fully programmable macrocell and variable product term assignment.
Macro cells offer a variety of programmable options for product and output. The programmable macrocell can also feed back to the array or use the output pins as inputs. The flexible PLD macrocell becomes a truly practical device for implementing logic functions. The first PLD is shown in Figure 1.6.
Figure 1.6 Schematic diagram of the first PLD
The PLD concept is further expanded to produce a CPLD. Similar to a PLD consisting of multiple PALs and macrocells, the CPLD contains multiple PLD logic blocks connected to I/O pins, connected to each other through a programmable interconnect architecture, as shown in Figure 1.7. This measure increases the amount of logic in a single device.
Figure 1.7 CPLD structure diagram
The logic blocks in a CPLD are often referred to as logic array blocks (LABs), and each LAB is like a PLD. CPLD LABs typically contain 4 to 20 macrocells. The programmable array in LAB is very similar to a PAL or PLD array.
However, the variable product term assignments in CPLDs and PLDs are different. Macrocells in CPLD LAB typically include additional AND gate logic that is fed back directly to the array. This extra logic can be used to form additional product terms called extensions. Additional product terms generated by the expansion logic can be used in the current macrocell to extend the logic functionality.
Other macro units can also share extensions. Thus, for a macrocell that requires a product term, only one product term is established, and it is not necessary to establish it each time. This is a more efficient way to reduce logic waste, as shown in Figure 1.8.
Figure 1.8 Macrocells in CPLD LAB
Note: The disadvantage of using extension logic is the extra latency caused by the extended product term, and the delay using the extension logic is known. Therefore, this should be considered when placing logic and performing timing analysis.
In addition to LAB, other structures in CPLD are similar to PAL and PLD, but the configuration is more advanced. The interconnection between LABs is referred to as a programmable interconnect array, ie PI or PIA. PI is similar to programmable arrays in PAL and PLD, using the same programming techniques. PI provides all the traces required for data transfer between LABs and between LAB and I/O pins.
With PI, any LAB input and output can be connected to any other LAB or I/O. This is the key to implementing a very flexible programmable device. Another improvement of CPLD over PLD is the addition of a separate I/O control module. In a PLD, the I/O pins are directly connected to the logic. In CPLD, PI separates the I/O pins from the main logic of the device. The I/O pins have their own control logic to implement a variety of features. Any pin has multiple I/O standards, input, output, or bidirectional operation, and does not require forcing certain pins to be used only as inputs.
The biggest advantage of CPLD over PLD is the number of logic and routing options. LAB logic and PI are fully programmable, offering great design flexibility in a single device. CPLD's I/O features and functions go far beyond the simple I/O of PLDs, providing more options and control over how I/O works.
Like PAL and PLD, the CPLD can be turned on instantaneously when it is powered on the board. They have a very low cost and take up very little board space. The non-volatile EEPROM programming architecture makes it ideal for use in system programming methods for testing and debugging without reprogramming the board when it is powered. Current Altera CPLDs include the MAX 3000 and 7000 Series devices, as well as the MAX II and MAX IIZ families.
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