After the project code is compiled, the following information is printed:
Info: Clock “CLK48M†has Internal fmax of 67.47 MHz between source register “GLUE_LGC:glue|MCLK†and desTInaTIon register “img_lgc:img|N2DSP†(period= 14.822 ns)
The signal from MCLK to N2DSP defines the maximum speed of the hour hand to only 67.47MHz.
See the following code snippet in the relevant code:
Always @( posedge CLK48M )
Begin
CLKDIV <<= CLKDIV + 1; //clock divider
End
Always @(posedge CLKDIV[5])
Begin
MCLKB3 <<= MCLK_EXT;
MCLKB2 <<= MCLKB3;
MCLKB <<= MCLKB2;
MCLK <<= MCLKB | MCLKB2 | MCLKB3;
End
This code segment is a simple anti-shake process for MCLK_EXT, which is equivalent to using a clock CLKDIV[5] derived from CLK48M.
MCLK is latched again in other modules using the CLK48M system clock, so it is equivalent to complete the conversion of CLKDIV[5] between the two CLK48M clocks, and then use the rising edge of CLKDIV[5] to trigger the conversion of MCLK. Then output to the destination register. This process takes a long time, and the time spent by CLKDIV[5] is obviously redundant.
Modify the code as follows:
Always @( posedge CLK48M )
Begin
CLKDIV <<= CLKDIV + 1; //clock divider
If (CLKDIV == 6'b100000)
Begin
MCLKB3 <<= MCLK_EXT;
MCLKB2 <<= MCLKB3;
MCLKB <<= MCLKB2;
MCLK <<= MCLKB | MCLKB2 | MCLKB3;
End
End
The two logic functions are the same, but since the CLK48M clock is used only after the modification, the logic uses CLK48M as the trigger clock, which saves the delay of the first-level flip-flop, thus greatly shortening the source-to-destination register. Delay. Increased maximum clock rate. The maximum frequency information of the CLK48M system clock after compilation is as follows:
Info: Clock “CLK48M†has Internal fmax of 77.08 MHz between source register “img_lgc:img|DATABUF[13]†and desTInaTIon register “img_lgc:img|CAM_D[6]†(period= 12.974 ns)
It can be seen that the maximum frequency of CLK48M can reach 77.08M, which is determined by the path between "img_lgc:img|DATABUF[13]" to "img_lgc:img|CAM_D[6]". Continue to optimize for this network later.
This method of using derived clocks is a mistake in many people's logic design (because it has a very serious impact on timing, so it is not an error here), because it is typical, so it is specially organized, hope Attracted the attention of the primary logic engineer.
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