Power Line MAC/PHY Integrated Transceiver INT51X1 and Its Application

Power Line Communication (PLC) technology is a communication technology that uses high-frequency data, voice, image and other multimedia service signals in the distribution network's medium/low voltage lines. The purpose is to provide users with a new type of low-voltage line. Broadband access scheme for No (new line); and medium voltage line to provide a reliable data transmission platform for distribution network automation. As the development prospects of this technology are very promising, as early as the early 1990s, some countries began to conduct research in this area, but due to the immature technology, the development speed is slow. Since the beginning of the 21st century, with the breakthrough of PLC technology, the development speed of power line communication technology has obviously accelerated. It is currently developing in the direction of practical use.

The power line is different from the ordinary communication line, and its channel has the characteristics of not constant and uncontrollable in the time domain. Therefore, it is necessary to adopt effective technical means of anti-interference, anti-impedance mismatch, anti-multipath fading, and solve the problem of signal conflict, and then it is possible to use the power line as the transmission medium, thereby realizing high-speed data communication. Multicarrier Orthogonal Frequency Division Multiplexing (OFDM) is an effective way to solve these problems. The technology utilizes the high-frequency spectrum resources of the power line to modulate the data with a plurality of mutually orthogonal carriers, and finally converts the serial data stream into parallel processing; the modulation and demodulation process can be implemented by DFT/IDFT using Fourier transform . Intellon's INT51X1 chip is the most complete OFDM processing chip available today. It is compliant with the HomePlug 1.0.1 technology standard and has a transfer rate of up to 14Mbps. Moreover, it integrates USB 1.1, Ethernet and MII/GPSI interfaces as well as ADC, DAC and AGC controllers, which is convenient to use, which provides an ideal solution for the research and development of PLC communication devices.

1 INT51X1's functional structure and main features

The INT51X1 is a MAC/PHY integrated transceiver dedicated to power lines. It uses Intellon's proprietary PowerPacket Orthogonal Frequency Division Multiplexing (OFDM) technology with 84 subcarriers and ROBO/DBPSK/DQPSK modulation; INT51X1 Subcarriers are allocated according to the signal-to-noise ratio of the transceiver to overcome the effects of noise and multipath fading; it does not require pilots to complete synchronization in a low SNR channel. Its internal structure is shown in Figure 1. It can be seen that it consists of an I/O module, a PowerPacket MAC module, a PowerPacket PHY module, and an ADC/DAC module.

In the INT51X1, the PowerPacket MAC module mainly completes the link layer function and is the core part of the chip. This module includes a reduced instruction set (RISC) processor core, an OFDM data processing, encryption/decryption algorithm and channel optimization algorithm. The program memory (ROM) also has a link sequence, a data memory (RAM), and two direct data transfer channels (DMA). All data sent from the user to the power line network or from the physical layer can be signal processed by the algorithm in the MAC module. The MAC uses the Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA) protocol to access the common power line channel and is supplemented by an automatic retransmission request ARQ and power packet priority mechanism to ensure transmission reliability. Moreover, since the power packet priority level can be flexibly set, the INT51X1 has strong burst processing capability. Allowing multi-frame transmission on the power line greatly reduces the requirements for network termination and maximizes network throughput, thus ensuring the shortest delay time and optimal signal stability. In addition, the MAC also has flow control capabilities. These features of the INT51X1 ensure excellent quality of service (QoS) for users on particularly harsh power line channels.

The PowerPacket PHY module is primarily used to implement physical layer functions, providing electrical means to establish, maintain, and tear down physical connections to ensure transparent transmission of bitstreams on the power line. This module consists of a physical layer logic sequence, a first-in, first-out (FIFO) stack corresponding to the MAC sub-layer DMA channel, and a forward analog channel. In addition, it also integrates the automatic gain control (AGC) of the external operational amplifier. Features. Its forward analog channel consists of a pair of high speed 10-bit A/D, D/A converters with a sampling speed of 50Mbps. The module's reference voltage is independent of on-chip and operates at low power. The op amp and filter are then connected and then connected to the power line via a power line coupling.

The I/O module integrates various interfaces between the MAC and the host and peripheral devices, so the functions are very rich. The interface with the host has a USB interface, a media independent interface MII or a universal serial interface GPSI (optional), a management data interface MDI; the interface with the peripheral has an E2PROM interface SPI, an emulation interface JTAG, and an LED interface for operational status monitoring. Among these interfaces, MII is a standard industrial interface, and its transmission/reception is performed in a four-bit parallel manner and synchronized by the MAC clock. At the same time, the MII also has a CSMA/CD protocol. GPSI is a flexible two-way serial interface with fewer interface lines than MII. When the host transmits data to the INT51X1 through the MII/GPSI interface, the data frame format is as follows:

<Interframe space> <preamble> <delimiter> <data> <frame check sequence>

The preamble is a 56-bit "1", "0" phase sequence for synchronization; a 1-byte delimiter is specified as D5H; the data data format follows the IEEE802.3 standard? The final frame check sequence is 4-byte CRC check result.

The host can easily access the internal control/status register of the INT51X1 through MDI, thus completing the setting of the INT51X1 and monitoring the real-time running status of the INT51X1. The control/status registers of the INT51X1 are 16-bit registers. The status register can reflect link status, transmission rate, preamble decision, auto-negotiation, fuzzy detection and other information in real time. The definition of the control register is shown in Figure 2. As can be seen from Figure 2, many functions can be realized through the control register.

After power-on, the initialization of the INT51X1 is completed by reading the data written to the E2PROM in advance via the SPI interface.

In addition to the above main features, PowerPacket's security performance is also very perfect, it uses DES's 56-bit key management method, in addition to the default key set by the INT51X1, the user can also customize the key to ensure power line transmission. Reliable and secure.

2 INT51X1 pin description

The INT51X1 is available in a μBGA package with 144 pins, a chip supply voltage of 3.3V, and a chip core supply voltage of 1.5V. The INT51X1 has three working modes: USB, PHY, and HOST/DTE. Some of the multiplexed signal pins have different function definitions depending on the mode. Taking the HOST/DTE mode as an example, the signal pins are defined as follows:

(1) Function of MII interface pin

MII-RX0~MII-RX3: receiving data lines;

MII-RXCLK: receiving clock line;

MII-RXDV: Receive data valid end;

MII-RX-ER: receiving error indication end;

MII-COL: conflict detection;

MII-TX0~MII-TX3: transmit data lines;

MII-TXCLK: transmit clock;

MII-TXEN: Transmit Enable;

MII-CRS: carrier sense;

MII-TX-ER: Send error.

(2) Function of MDI interface pin

MII-MDIO: Manage data input and output;

MII-MDCLK: manages the data I/O clock;

SPI: interface pin;

SPI-DO: The data can be output to the E2PROM through this terminal;

SPI-DI: Data is read in from E2PROM;

SPI-CLK: SPI clock;

SPI-CS: Strobe E2PROM.

The other signal lines in the chip are the same in all three modes, including 26 control/data lines of the analog front-end AFE (including ADC input, DAC output, AGC control of the op amp, etc.), 3 LED lines, and 5 JTAG lines. 2, clock 2, test line 2, and multiple power and ground; the choice of three modes can be determined by the state of the two pins MODE0 and MODE1.

Due to space limitations, detailed information about the pins will not be detailed here. Those who are interested can refer to the relevant materials.

3 INT51X1 application in power line communication

As a power pack integrated transceiver, the INT51X1 can achieve high-speed data transmission with high-frequency power lines. Since the chip is highly integrated with the data processing function of the power package and the external related interface, it is only necessary to perform simple initialization without complicated programming, and is very convenient to use. Now the author studies the OFDM communication system of medium voltage distribution network as an example to introduce the application of INT51X1.

3.1 Mode selection

The INT51X1 USB, PHY or HOST/DTE modes can be selected by setting the INT51X1 pins MODE0 and MODE1. The specific selection methods are listed in Table 1.

Table 1 Working mode selection method

The USB mode actually connects the INT51X1 as a USB device to the USB host. The PHY mode connects the PHY51X1 to an Ethernet physical layer device PHY to a microprocessor or Ethernet controller. The HOST/DTE mode treats the INT51X1 as a network host or a data terminal and then connects to an Ethernet PHY or other data device via the MII interface. In this way, the INT51X1 acts as a bridge between the Ethernet and the power line network, thereby connecting those data devices to the power line network.

The application of this design is to use the medium voltage power line to communicate all the distribution automation devices on the medium voltage distribution network to build a communication network for distribution network automation. Obviously, this design should choose HOST/DTE mode.

3.2 Communication terminal design

The distribution automation device should be equipped in the vicinity of the distribution network. Its task is to collect the operating parameters of the distribution line and various power equipment and send it to the distribution automation main station, and receive the relevant control commands of the automation main station. To control the line and power equipment. In order to transmit these parameters and commands with the power line, the author designed a communication terminal as shown in FIG.

This design is designed with an analog front-end module (AFE Module) on the INT51X1 power line side. The module contains a gain-adjustable transmit amplifier and receive amplifier. The transmit and receive branches have an LC band-pass filter. The bandpass filter has a passband of 4 to 21 MHz, which is a frequency band occupied by OFDM modulation. Coupler is a special device that connects the AFE to the power line. The main function is to transmit high-frequency signals with low insertion loss, while preventing the power line current of the power line from entering the communication terminal. On the user side of the INT51X1 is TI's high-speed DSP (TMS320VC5471), which embeds the MII interface, and connects to the INT51X1, and uses the UART serial port to connect to the distribution automation device (Data Equipment in the figure). The data transmitted by the distribution automation device is encapsulated by the DSP in the aforementioned MII data frame format, and transmitted to the INT51X1 via the MII interface, and then converted into a PowerPacket to be sent to the power line, and then received by the destination communication terminal. The PowerPacket sent from the power line to the terminal is unpacked and converted into MII frames by the INT51X1, and finally transmitted to the automation device via the DSP.

4 Conclusion

The INT51X1 is a highly integrated single-chip power line transceiver that is a replacement for the INT5130+INT1000 chipset and is currently the mainstream product for developing power line OFDM communications. The chip is powerful, flexible, and reliable. However, according to the author's experiment, the transmission rate can only reach about 8Mbps, but it can't reach the theoretical 14Mbps. However, for power line communication, because the bandwidth requirement is not particularly large, it can fully meet the application needs.

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