Research and implementation of creative ear pattern recognition system

Project background and feasibility analysis

Project name, main content of the project and current progress

Project Name: Research and Implementation of Earprint Recognition System Based on FPGA

Project content: mainly composed of three aspects: embedded technology, ear pattern acquisition technology, ear pattern recognition algorithm.

Current progress: The algorithm is in the debugging phase on other platforms, and the hardware is in the modular design phase.

Discussion of key technologies and innovations of the project

Key Technologies: How to use FPGA to perform data processing to improve the quality of input earprint images to improve the accuracy of feature extraction.

Innovation: Advanced SOPC technology simplifies system board design, enhances system stability, and uses VHDL programming to achieve high-speed data acquisition through hardware to reduce the burden on the processor, and finally achieve fast ear pattern image acquisition through FPGA hardware. The DSP performs data processing to improve the quality of the input earprint image to improve the accuracy of feature extraction.

Technical maturity and reliability discussion:

Hardware: The Xilinx Spartan-3E FPGA's DSP includes a set of floating-point operators, a DVB FEC encoder core, and enhanced key features of the existing core, including the latest ISE 7.1i development tools. Full support for better performance for performance, silicon utilization, or both.

Algorithm aspect: The distribution of elements such as contours, creases, wings, wrinkles, spots, birthmarks, etc. in the ear pattern features lifetime invariance and uniqueness for the ear pattern of a particular person. It is the clearest and most visible in the typical area of ​​the ear and is the main parameter for ear pattern matching. The extraction process includes steps such as pseudo feature point elimination, external shape detection, internal structure, spots, wrinkles, and detection and classification of crease lines to facilitate feature matching. It can be characterized by the Fourier coefficient of the auricle curve, or an algorithm such as principal component analysis or Zernike moment. Feature extraction algorithms need to be able to adapt to common realities such as noise, distortion, displacement, rotation, defects, and deformation.

Through the above analysis, the reliability of the project has been guaranteed. I believe that with the rich development experience of our team, the project will be more mature in technology and achieve the expected results.

Project implementation plan

1. Basic functional block diagram and description of the program

Ear pattern recognition

The sensor extracts the characteristics of the ear pattern contained in the shape structure of the ridge, and the analog signal amount from the sensor is controlled by the FPGA acquisition control module to convert the A/D converter into a digital signal, and the DSP processor passes the digital signal through the binary value. The earprints that are in contact with the sensor are highlighted by useful information, and the discontinuous earprint information block is marked to obtain the edge of the auricle for feature extraction. Finally, the Fourier coefficients of the auricle curve are characterized by the corresponding algorithm, or the principal component analysis method, the Zernike moment algorithm and the like can be used. The feature extraction algorithm needs to be able to adapt to common realities such as noise, distortion, displacement, rotation, defect, and deformation.

2. The required development platform

(1) Basic functions, functions, and interfaces required to implement this solution:

The platform contains A/D, and the sampling clock can reach 80MHz.

The FPGA clock rate on the platform is at least 100MHz;

The FPGA on the platform has multiple DCMs;

Support DSP;

The platform contains DRAM, SRAM or FLASH memory.

(3) The required target FPGA development platform, a brief description of why this platform is needed

The target platform is the Spartan-3E 500,000-door development platform for the following reasons: This project requires high-speed data acquisition and DSP image processing. It requires a hardware processing platform with high processing speed and rich logic resources to implement the SOPC system solution. The Spartan-3E 500,000-door development platform has strong DSP processing capabilities and rich on-chip resources, so it can be used in this design;

Development tools required include MATLAB/Simulink, ModelSim, XilinxISE, EDK, and more.

2. Modules to be developed during the implementation of the program

The main modules of the function that need to be developed and developed in this scheme are as follows:

High-speed A/D acquisition module

USB module

LCD display module;

Touch screen module;

Storage module

Adopt modular development.

3. The final performance indicators of the system

By comparing the degree of similarity between a set of earmark feature points extracted on the spot and a set of earmark feature points in the originally established database. The cost function (or matching energy) is usually used to indicate the degree of similarity, and the appropriate threshold will give a judgment as to whether the two sets of ear pattern features are from the same ear of the same person.

Other resources needed

1. Design input and output function daughter board

Image acquisition signal amplification circuit, keyboard input expansion board.

2. Test equipment

Including DC stabilized switching power supply, multimeter, digital oscilloscope, logic analyzer and other common equipment.

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